AMD Postpones “Bulldozer” Launch until Q3 2011
To the disappointment of many, rumors have been swirling today at Computex that AMD had decided to delay the launch of their new Bulldozer architecture until at least July. This means the Zambezi chips which were destined for desktop platforms will also be pushed back.
Bulldozer is set to be a redesign of AMD’s processor architecture, the last occurring in 2003 with the launch of the Athlon 64/Opteron processors. The Bulldozer chip will contain two 128 bit FPUs which can be combined into one 256 bit FPU if need be. It will also feature a new shared L2 cache within the architecture, and two integer cores with 4 pipelines each, called the Bulldozer module.
What makes this especially unique is the operating system is supposed to recognize each of these modules as two physical cores and an 8 core chip will feature 4 of these modules.
While this redesign does seem nothing short of revolutionary, AnandTech is reporting from Computex that performance issues with the B0 and B1 stepping chips have pushed back the launch. These chips were suffering from performance issues, rumors were that they weren’t meeting desired (read: beating Intel’s new Sandy Bridge chips) speeds, though AMD believes that these problems can be remedied with a new chip stepping.
AMD was expected to launch four processors based on the Bulldozer architecture at Computex with prices ranging from $190-$320.
This is not the first time AMD has had to make last minute revisions to processor architecture because of performance issues. In 2007, with the launch of their Phenom line, a flaw was discovered in the Translation Lookup Buffer (TLB) that would cause system lockups. Although AMD released a workaround, users complained that they would experience a performance drop of up to 10%. AMD fixed the problem with a new chip stepping, though it arrived months after the initial release.
Bulldozer is set to be a redesign of AMD’s processor architecture, the last occurring in 2003 with the launch of the Athlon 64/Opteron processors. The Bulldozer chip will contain two 128 bit FPUs which can be combined into one 256 bit FPU if need be. It will also feature a new shared L2 cache within the architecture, and two integer cores with 4 pipelines each, called the Bulldozer module.
What makes this especially unique is the operating system is supposed to recognize each of these modules as two physical cores and an 8 core chip will feature 4 of these modules.
While this redesign does seem nothing short of revolutionary, AnandTech is reporting from Computex that performance issues with the B0 and B1 stepping chips have pushed back the launch. These chips were suffering from performance issues, rumors were that they weren’t meeting desired (read: beating Intel’s new Sandy Bridge chips) speeds, though AMD believes that these problems can be remedied with a new chip stepping.
AMD was expected to launch four processors based on the Bulldozer architecture at Computex with prices ranging from $190-$320.
This is not the first time AMD has had to make last minute revisions to processor architecture because of performance issues. In 2007, with the launch of their Phenom line, a flaw was discovered in the Translation Lookup Buffer (TLB) that would cause system lockups. Although AMD released a workaround, users complained that they would experience a performance drop of up to 10%. AMD fixed the problem with a new chip stepping, though it arrived months after the initial release.
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